library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is
  port(
    D   : in  std_logic;
    E   : in  std_logic;
    CLK : in  std_logic;
    Q   : out std_logic
  );
end ffd;

architecture behavioral of ffd is
begin

  process(D, E, CLK)
  begin
    if(CLK = '1' and CLK'event and E = '1') then
      Q <= D;
    end if;
  end process;

end behavioral;
